74ls164 shift register introduction (features, pins, parameters, timing)

July 25, 2023

Introduction to 74ls164 Shift Register

The 74ls164 is an 8-bit edge-triggered shift register that serially inputs data and then outputs it in parallel. Data is serially input through one of two inputs (DSA or DSB); either input can be used as a high level enable to control the data input of the other input. The two inputs are either connected together or the unused inputs are tied high and must not be left floating.

The 8-bit shift register features an AND gate enable control serial input and an asynchronous reset input. The enable control input can control unwanted input data signals to a low level. When the reset signal is low, the output is low regardless of the state of other signals; when the reset signal is high, the register shifts the input data sequentially from the first bit on the rising edge of each clock signal. .

74ls164 shift register features

Wide operating voltage range: 2V-6V;

The output can drive loads up to 10 LSTTLs;

Tpd typical value = 20ns;

The output current is ±4mA when the operating voltage is 5V;

And the gate enable control serial port input;

Both the clock and the serial input have a buffer circuit;

Direct reset.

74ls164 shift register pin diagram and pin function
74ls164 shift register introduction (features, pins, parameters, timing)
74ls164 shift register introduction (features, pins, parameters, timing)
74ls164 shift register main parameters

Limit parameter

74ls164 shift register introduction (features, pins, parameters, timing)

Electrical characteristics

74ls164 shift register introduction (features, pins, parameters, timing)

Conversion characteristics

74ls164 shift register introduction (features, pins, parameters, timing)

The scope of work

74ls164 shift register introduction (features, pins, parameters, timing)

[1] For DIP14 package: Ptot linearly decreases at a rate of 12 mW/K over 70 °C.

[2] For SO14 package: Ptot linearly decreases at a speed of 8 mW/K over 70 °C.

[3] For SSOP14 and TSSOP14 packages: Ptot linearly decreases at speeds of 5.5mW/K over 60°C.

[4] For the DHVQFN14 package: Ptot linearly decreases at a speed of 4.5 mW/K over 60 °C.

74ls164 shift register logic block diagram and timing diagram
74ls164 shift register introduction (features, pins, parameters, timing)

74ls164 shift register logic block diagram
74ls164 shift register introduction (features, pins, parameters, timing)

74ls164 shift register timing diagram

Timing requirements

74ls164 shift register introduction (features, pins, parameters, timing)


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