Recently, I talked with colleagues about the impact of the data bus width and alignment on the program efficiency under the ARM platform. When defining the structure data type, in order to improve the system efficiency, we should pay attention to the principle of word length alignment. Just a little touch and talk with everyone. Here is mainly to explain what the so-called alignment is? How to align? Why is the efficiency difference caused by alignment or alignment? 1. First look at the following example: #include #pragma pack(4) Struct A { Char a; Int b; }; #pragma pack() #pragma pack(1) Struct B { Char a; Int b; }; #pragma pack() Int main() { A a; Cout<(a);> B b; Cout<(b);> } The default vc I remember is 4 byte alignment ADS is a byte alignment, because it is c / c + + community everyone is familiar with the PC I will talk about the alignment under the PC. If you have a problem with the PC for too long, don't hesitate to say it directly. You can see that the results of 4-byte alignment and 1-byte alignment under ms vc are completely different. Why are 8 and 5 respectively? What is the result? This is the role of byte alignment on x86. To speed up program execution, some architectures are designed in an aligned manner, usually with word lengths as alignment boundaries. For some structure variables, the entire structure is aligned to the largest alignment boundary of the internal member variables, such as A, and the entire structure is bounded by 4, so sizeof(a) is 8, not 5. If the members of A in the original our concept will be stored one by one, only char + int should be only 5 bytes. This difference is due to alignment. However, we can see that A's alignment wastes 3 bytes of storage space than B. Then why should we take alignment? That's because the alignment and misalignment of the architecture is a trade-off in time and space. Byte alignment saves time. It should be the designer's consideration of using space for time. Why does alignment improve efficiency and save time? I think the focus of everyone's understanding is here. The bus width is 32 bits under our common PC. 1. If the bus width is aligned Then all read and write operations are to obtain a <= 32-bit data can be guaranteed to be transferred on the data bus at one time. No extra consumption |1|2|3|4|5|6|7|8| Starting from 1 is the starting position of a, and 5 is starting to be the position of b. If accessing a once on the bus transfer 8 bits other 24 bits are invalid When accessing b, it is transmitted 32 times on the bus. Read and write are complete Insert the read operation first put the read address on the address bus and then the next clock cycle and then from the outside It takes two cycles to read back the data on the memory interface and return it through the data bus. And the write operation once writes the address and data to the corresponding bus. Read operation is half slower than write operation 2. We see if the address is not aligned when accessing the data. |1|2|3|4|5|6|7|8| At this point, the address of a does not change to 1 and because it is not aligned, the position of b is at 2 At this time, the access brings efficiency problems. When accessing a, there is no problem or reading a byte. But the 2 addresses are not the bus width alignment. The CPU will generate an error at this address. Such as sparc, MIPS. They are mandatory for alignment in hardware design. An error must occur on an unaligned address But x86 is support for non-aligned access. It spliced ​​the results through multiple visits. The specific method is to read back the last three bytes 234 from the address. Then read back a byte 5 and 234 by 5 address to form a complete int, that is, b return Everyone sees that the operation is more than three times more expensive. It is obviously more efficient when the word length is aligned. Inadvertently, this efficiency is only caused by accessing multiple bytes. If the byte operation is still performed, the efficiency is not much worse. Current development generally pays more attention to performance, so there are two different ways to handle alignment problems: 1) There is a way to use space for time to be explicitly inserted into reserved members: Struct A{ Char a; Char reserved1[3]; //Use space for time Int b; }a; 2) Just write it, and leave it to the compiler for automatic alignment. There is also a way to define logically related data together. Many of the hidden dangers of alignment in the code are implicit. For example, when forcing a type conversion. Here is an example: Unsigned int i = 0x12345678; Unsigned char *p=NULL; Unsigned short *p1=NULL; p=&i; *p=0x00; P1=(unsigned short *)(p+1); *p1=0x0000; The last two lines of code, accessing the unsignedshort type variable from the odd boundary, obviously do not meet the alignment requirements. On x86, similar operations only affect efficiency, but on MIPS or sparc, it may be an error.
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