At low frequencies, the effect of vias is small. However, in high-speed series connections, the vias can ruin the entire system. In some cases, at 3.125 Gbps, they can use a nice, wide hole. Turn it into a pillar at 5 Gbps. Understanding the root cause of via via limitations is to optimize their design and verify their first steps. This article will describe a simple via-hole modeling and simulation process from which you can get some key points to optimize your design. You can't happen to design an interconnect that can work at 2Gbps or higher. In order to achieve the target data transfer rate, the interconnect must be optimized. In many cases, the vias may become the termination of a high speed series unless the vias are optimized to have a smaller effect. The root cause of the differential via problem is mainly from three aspects, 90% is vias vias, 9% is from vias, and 1% is from return vias. The so-called via process is to solve these three key points. The first step is to minimize the length of the via root. As a rule of thumb, the length of the via root, in mils, should be less than 300 mils/BR, and Br is the rate of Gbps. The second step is to bring the penetrating portion of the hole path close to the impedance of the line, typically 100 ohms. The impedance difference between the different vias is usually less than 100 ohms, so if possible, minimize the diameter, increase the pitch, clear the holes, increase the vias on the layers, and remove all useless pads. In addition, the surrounding line impedance can be reduced. In general, even a 65 ohm impedance difference will result in an insertion loss of less than -1 dB, let alone in a 15 GHz, 100 ohm difference system. Finally, placing adjacent return vias near the signal space will help control the signal noise generated by ordinary signals being transmitted through the system. For different systems, the introduction of return via is not necessarily critical to signal quality, although it is always a good habit. Once these key points are optimized, considering the real situation, we always have the same problem, will he work normally? Have I done enough to handle the vias? One way to answer this question is to set up a test device and take measurements. This is the practice of "testing performance." The cost is very high, time and resources, but the end result will be your confidence to greatly improve the reliability of the product. Another approach is to simulate the final design before determining the hardware and submission build. The only one that accurately simulates differential vias is the use of three-dimensional full-wave electromagnetic field solvers, such as those offered by Agilent Technologies and CST. These tools have proven to be very accurate and easy to explain the different and common effects, including the effects from the return path, but are generally more complex. The tool's S-number performance module can be used in many system simulators to predict first- and second-level effects. This is a perfect process. However, for some via structures, the differential impedance characteristic can be approximated by a very simple module. In this way, analytical prefabrication can be shortened to minutes instead of hours or even days. It also provides an in-depth analysis of how many possible problems the vias face, as well as features that are relatively important to the design. Therefore, when evaluating the via hole effect in high-speed series, we always use a simple model first. The return is huge compared to the energy invested. First, differential vias can be modeled as a uniform differential pair with differential impedance and dielectric constant. It is divided into two or three equal parts depending on how the signal layer enters and leaves the via. The only difference between these parts is their length. They all have the same differential impedance or odd mode impedance, as well as the dielectric constant. The differential impedance of these two vias can be roughly estimated based on the typical resistance analysis model of twin rods. As shown in Figure 1 The differential impedance can be estimated by the twin rod model: Z0 = differential impedance (ohms) D = via diameter (mils) s = center to center spacing (mils) Dk = effective dielectric constant of approximately 4–6.5 For example, if glass weave and resin have a dielectric constant of 5, a gap of 60 mils, and a via diameter of 30 mils, then the differential impedance is: The vias are typically less than 100 ohms. What kind of value is acceptable to us? The most common answer to the signal integrity problem is "It depends." If the -1dB insertion loss is acceptable, the via impedance can be as low as 65 ohms, but still meets 100 ohms. This performance specification. In general, only using the electrical model to simulate the entire process will give you a confident answer. This simple differential pair model is a necessary element to build confidence in your design before you build it.
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