Priority is that interrupts with high preemptive priority can be responded to during interrupt processing with low preemptive priority, ie interrupt nesting, or interrupts with high preemptive priority can be nested with low preemptive priority Interrupted.

When the preemptive priorities of the two interrupt sources are the same, the two interrupts will have no nesting relationship. When one interrupt arrives, if another interrupt is being processed, the subsequent interrupt will wait until the previous interrupt is processed. Can be processed. If the two interrupts arrive at the same time, the interrupt controller decides which one to process first based on their response priority level; if their preemptive priority and response priority are equal, then according to their rank in the interrupt table The order determines which one to process first.

The 68 external interrupt channels that the STM32 can support are already fixedly assigned to the corresponding external devices. Each interrupt channel has its own interrupt priority control byte PRI_n (8 bits, but only 4 bits are used in STM32, the upper 4 bits are valid), and the 8-bit interrupt priority control word (PRI_n) is configured for every 4 channels. A 32-bit priority register (PriorityRegister). The 68 channel priority control words form at least 17 32-bit priority registers, which are an important part of the NVIC registers.

For this 4-bit interrupt priority control bit, it must also be divided into two groups: starting from the high bit, the front is the bit that defines the preemptive priority, and the latter is used to define the sub-priority. The 4bit packet combination can have the following forms:

Group 0: All 4 bits are used to specify the response priority

Group 1: The highest 1 bit is used to specify the preemptive priority, and the lowest 3 bits are used to specify the response priority.

Group 2: Up to 2 bits are used to specify preemptive priority, and the lowest 2 bits are used to specify response priority

Group 3: Up to 3 bits are used to specify preemptive priority, and the lowest 1 is used to specify response priority

Group 4: All 4 bits are used to specify preemptive priority

Since we use the library functions of STM32, here is how to use the library functions to set the required priority.

You can choose which priority grouping method to use by calling the function NVIC_PriorityGroupConfig() in the firmware library of STM32.

This function is in the helper file's standard peripheral driver CMSIS\CMSIS_Expord_FuncTIon;

The parameters of this function are as follows:

NVIC_PriorityGroup_0 =》 Select Group 0

NVIC_PriorityGroup_1 =》 Select Group 1

NVIC_PriorityGroup_2 =》 Select Group 2

NVIC_PriorityGroup_3 =》 Select Group 3

NVIC_PriorityGroup_4 =》 Select Group 4

It should be noted here that after the system reset is initialized, the 0th priority grouping is used by default.

The next step is to specify the priority of the interrupt source . Here is a simple example of how to specify the preemptive priority and response priority of the interrupt source:

If the application is stored in ROM and there is no need to change the exception service, we can encode the entire vector table to the beginning of the ROM (the segment starting at address 0). In this case, the offset of the vector table will always be 0, and the interrupt vector is always in ROM, so the above example can be greatly simplified, just 3 steps:

1. Establish a priority group

2. Assign a priority to the interrupt

3. Enable the interrupt

// Select to group 1 using priority grouping

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);

// Enable EXTI0 interrupt initialization to use the same structure as GPIO

NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQChannel;

NVIC_InitStructure.NVIC_IRQChannelPreempTIonPriority = 1; // Specify preemptive priority level 1

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; // Specify response priority level 0

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

// enable EXTI9_5 interrupt

NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQChannel; / / here refers to the external interrupt 9-5 line

NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; // Specify preemptive priority level 0

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; // Specify response priority level 1

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

The points to note are:

1) If the specified preemptive priority level or response priority level exceeds the range defined by the selected priority grouping, an unexpected result may be obtained; the range here refers to the group 4 preemptive priority level 0~15, The second set of preemptive priority ranges from 0 to 3, and the response priority is 0~3; the remaining groups are similar.

2) There is no nested relationship between the interrupt sources with the same preemptive priority level;

3) If an interrupt source is specified as a preemptive priority level and no other interrupt source is in the same preemptive priority level, then any valid response priority level can be specified for this interrupt source. In other words, the preemptive priority must be interrupted to interrupt the interrupt priority.

Switch total interruption:

In STM32/Cortex-M3, interrupts are enabled or disabled by changing the current priority of the CPU.

PRIMASK bit: Only NMI and hard fault exceptions are allowed, and other interrupts/exceptions are masked (current CPU priority = 0).

FAULTMASK bit: Only NMI is allowed, all other interrupts/exceptions are masked (current CPU priority = -1).

In the STM32 firmware library (stm32f10x_nvic.c and stm32f10x_nvic.h) four functions are defined to operate the PRIMASK bit and the FAULTMASK bit, changing the current priority of the CPU to achieve the purpose of controlling all interrupts.

The following two functions in the new library are equivalent to closing the total interrupt:

Void__disable_irq (void);

Void __disable_fault_irq (void);

The following two functions are equivalent to the open total interrupt:

Void __enable_irq (void);

Void __enable_fault_irq (void);

The above two sets of functions need to be used in pairs and cannot be used interchangeably.

E.g:

the first method:

PRIMASK is used to disable all exceptions except NMI and hard fault, which effectively changes the current priority to 0 (the highest priority in the programmable priority).

Void__disable_irq (void);//Close total interrupt

Void __enable_irq (void);//open total interruption

__set_PRIMASK(1);

__set_PRIMASK(0);

The second method:

FAULTMASK is even more absolute, it changes the current priority to ‐ 1 . As a result, even hard faults are masked. The usage scheme is similar to that of PRIMASK. However, it should be noted that FAULTMASK will be automatically cleared when it exits abnormally.

Void __disable_fault_irq (void); //Close the total interrupt

Void __enable_fault_irq (void);//open total interruption

__set_FAULTMASK(1);

__set_FAULTMASK(0);

Often used

Void__disable_irq (void);//Close total interrupt

Void __enable_irq (void);//open total interruption

The PreemptionPriority mentioned in the library function means preemptive priority, and subPriority means response priority, also called sub-priority. What is the preemptive priority?

As the name implies, when the preemptive priority is different, the preemptive priority is high, and the preemptive priority is low, which is called nesting! It is not possible to interrupt nesting between the same preemptive priorities. For example, if the system uses the fourth group priority grouping method, it means that all 4 bits are used to specify the preemptive priority, that is to say, there are 16 levels of preemptive priority. By assigning an interrupt priority to the required interrupt source, you can achieve the high-priority interrupt function you want to start before the low-priority interrupt function is executed, that is, interrupt nesting. Complete 1 interrupt and 15 levels of nesting.

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