First, the MSP430 development environment is established

1. Install the IAR dor msp430 software with the USB emulator driver.

2. Insert the USB emulator and drive the /drivers/TIUSBFET to select the installation directory.

3. Create a project, select the "option" option, set

a, select the device, select the target device in the "Target" tab of the "General" item

b. Select the output simulation. In the "Output" tab of the "Linker" item, select the output "Debug information for C-SPY" to output the debug.

Information is used for simulation.

c. If you select "Other", the Output drop-down box selects "zax-m" to output the hex file for burning. Note that the simulation cannot be performed at this time.

d, select the "Setup" tab of the "Debugger" item, and select "FET Debugger" from the "Driver" drop-down box.

e, select the "Setup" tab of the "FET Debugger" item, and select "Texas Instrument USB-I" in the "Connection" drop-down box.

4. The interface of the emulator is "GND, RST, TEST, VCC" from left to right.

Second, IO port

The digital input/output ports have the following features:

Each input/output bit can be programmed independently.

Allows arbitrary combination of input and output.

All 8 bits of P1 and P2 can be set to interrupts respectively.

Input and output data registers can be operated independently.

Pull-up or pull-down resistors can be set separately.

When introducing these four I/O ports, I mentioned a "pull-up resistor". So what is the pull-up resistor? What role does he play? It is said that the resistor is of course a resistor. When input, the pull-up resistor pulls its potential high. If the input is low, it can supply the current source. Therefore, if the P0 port is in the high-impedance state if it is used as an input, only one external pull-up resistor can be effective.

(The following x is 1 for P1, 2 for P2, and so on)

1. Select pin function -- PxSEL, PxSEL2

PxSEL2 PxSEL pin function

0 0 is used as IO port

0 1 is used as the first function pin

1 0 Reserved, refer to the manual of the specific model

1 1 used as the second function pin

When the set pin is used as a peripheral function, the chip does not automatically set the input/output direction of the pin. According to this function, the user sets the direction register by himself.

PxDIR.

2. Select Pin Input/Output Direction -- PxDIR

Bit = 0: input

Bit = 1: output

3. Select whether the pin enables the pull-down resistor -- PxREN

Bit = 0: not enabled

Bit = 1: enable

4. Output Register -- PxOUT

Bit = 0: Output low or pull down

Bit = 1: Output high or pull up

5. Pin Status Register -- PxIN

Bit = 0: Pin is currently low

Bit = 1: Pin is currently high

The "second function" you said should refer to the function of the peripheral module. Select the "second function" with the module, and select the "first function" without the module. It can be selected by setting the PxSEL register. A bit writes "0" as I/O; writing "1" as "second function". Set to the second function when using the comparator (on-chip peripheral module). Of course, if you use an off-chip comparator to send the high and low levels (1 or 0) of its output to the MSP430, then select the "first function".

Http://zhidao.baidu.com/question/172451580.html?an=0&si=3

3.Base clock module

One or four clock oscillation sources

1. LFXT1CLK: External crystal or clock 1 Low frequency clock source Low frequency mode: 32768Hz High frequency mode: (400KHz-16MHz)

2, XT2CLK: external crystal or clock 2 high frequency clock source (400KHz-16MHz)

3, DCOCLK: internal digital RC oscillator, reset value 1.1MHz

4, VLOCLK: internal low power oscillator 12KHz

Note: MSP430x20xx: LFXT1 does not support HF mode, XT2 does not support, ROSC does not support.

Two, three system clocks

1, ACLK: Auxiliary Clock

Reset: LF mode of LFXT1CLK, internal capacitance 6pF

Frequency division: 1/2/4/8

Clock source: LFXT1CLK/VLOCLK.

Uses: Independent peripherals, generally used for low-speed peripherals

2, MCLK: master clock

Reset: DCOCLK, 1.1MHz

Frequency division: 1/2/4/8

Clock source: LFXT1CLK/VLOCLK/XT2CLK/DCOCLK

Uses: CPU, system

3, SMCLK: subsystem clock

Reset: DCOCLK, 1.1MHz

Frequency division: 1/2/4/8

Clock source: LFXT1CLK/VLOCLK/XT2CLK/DCOCLK

Uses: Independent peripherals, generally used for high-speed peripherals

Third, the register

1, DCOCTL: DCO control register (read and write)

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DCOx: Define one of 8 frequencies, which can adjust the frequency of DCOCLK in stages, and the difference between the two adjacent frequencies is 10%. And the frequency is injected into the DC generator.

Current definition.

MODx: Bit adjuster selection. These bits determine the number of times a high frequency segment fDCO+1 is inserted during 32 DCOCLK cycles. when

DCOX=7, which is the highest frequency, and MODx cannot be used as the frequency adjustment.

2. BCSCTL1: Basic Clock System Control Register 1

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XT2OFF: Whether to turn off XT2

0: Open XT2, 1: Turn off XT2

XTS: XT2 mode selection

0: LF mode (low frequency mode), 1: HF mode (high frequency mode)

DIVA: ACLK crossover selection 0-3 corresponds to 1/2/4/8 division

RSELx: Select 16 nominal frequencies in the DCO, corresponding to 16 internal resistors

0-15 corresponds to the frequency from low to high. When DCOR=1, it means that the external resistor is selected, so RSELx is invalid.

3, BCSCTL2: basic clock system control register 2

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SELMx: Select the clock source for MCLK

0: DCOCLK

1:DCOCLK

2: XT2CLK is used when the XT2 oscillator is on-chip. Use LFXT1CLK or VLOCLK when the XT2 oscillator is not on-chip

3: LFXT1CLK or VLOCLK

DIVMx: MCLK frequency division selection 0-3 corresponds to 1/2/4/8 frequency division

SELS: Select the clock source for SMCLK

0: DCOCLK

1: XT2CLK is selected when the XT2 oscillator is present, and LFXT1CLK or VLOCLK is used when the XT2 oscillator is not present.

DIVSx: SMCLK frequency division selection 0-3 corresponds to 1/2/4/8 frequency division

DCOR: 0: DCOCLK uses internal resistor, 1: DCOCLK uses external resistor

4, BCSCTL3: basic clock system control register 3

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XT2Sx: XT2 range selection

0:0.4-1MHz crystal or oscillator

1:1-3MHz crystal or oscillator

2:3-16MHz crystal or oscillator

3: 0.4-16MHz external digital clock source

LFXT1Sx: Low frequency clock selection and LFXT1 range selection. Select between LFXT1 and VLO when XTS=0. When XTS=1

Select the frequency range of LFXT1.

0: 32768Hz crystal on LFXT1

1: reserved

2: VLOCLK (retained on MSP430X21X1 devices)

3: External digital clock source

XCAPx: Oscillator capacitor selection. These bits select the effective capacitance for LFXT1 when XTS=0.

0:1pF

1:6pF

2:10pF

3:12.5pF

XT2OF: Does the XT2 oscillator fail?

0: active, working

1: invalid, not working properly

LFXT1OF: Does the LFXT1 oscillator fail?

0: active, working

1: invalid, not working properly

5, IE1: interrupt enable register 1

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OFIE: Oscillator failure interrupt enable. This bit enables the OFIFG interrupt enable. Due to other bits of IE1

Used for other modules, so use the BIS.B or BIC.B instructions to set or clear the bit ratio

More suitable with MOV.B or CLR.B.

6, IFG1: interrupt flag register 1

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OFIFG: Oscillator failure interrupt flag. Since the other bits of IFG1 are used for other modules,

Use the BIS.B or BIC.B instructions to set or clear this bit than to use MOV.B or

CLR.B is more suitable.

0: no interrupts that are not responding

1: There are interrupts that are not responding

Fourth, DCO frequency

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4 frequencies with a calibration accuracy of ±1%

4. Timer TA

First, the clock source

1. Clock source: ACLK/SMCLK External TACLK/INCLK

2. Frequency division: 1/2/4/8 When (Note: when the TACLR is set, the divider is reset)

Second, the counting mode

The timer count mode can be set by setting MCx

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1, stop mode: stop counting

2, monotonically increasing mode: the timer cyclically increases from 0 to TACCR0 value

Period: TACCR0

CCIFG: Triggered when Timer counts TACCR0 value

TAIFG : Triggered when Timer counts to 0

3. Continuous mode: The timer loop is continuously increased from 0 to 0xFFFF.

Period: 0x10000

TAIFG : Triggered when Timer counts to 0

4, increase and decrease mode: the timer counts up to TACCR0 and then counts down from TACCR0 to 0

Period: 2 times the value of TACCR0

CCIFG: Triggered when Timer counts TACCR0 value

TAIFG : Triggered when Timer counts to 0

Third, timer A TACCRx comparison mode (for output and generate timing interrupt)

1, setting: CAP = 0 to choose to compare

2. Output signal: The compare mode is used to select the PWM output signal or to interrupt at a specific time interval. When TAR counts

When going to the value of TACCRx:

a, the interrupt flag CCIFG=1;

b, internal signal EQUx=1;

c, EQUx affects the output signal according to the output mode

d, the input signal CCI is latched to SCCI

Each capture comparison module contains an output unit. The output unit is used to generate a signal such as PWM. Each output unit can be based on

EQU0 and EQUx produce signals in 8 modes.

3, interrupt

TimerA has 2 interrupt vectors:

a, TACCR0 CCIFG TACCR0 interrupt vector

b. TAIV Interrupt Vectors for all other CCIFG and TAIFG

In capture mode, the CCIFG flag is set when the value of a timer is captured in the corresponding TACCRx register.

In compare mode, the CCIFG flag is set if the TAR counts to the corresponding TACCRx value. Software can be cleared or placed

Bit any CCIFG flag. When the CCIE and GIE of the response are set, the CCIFG flag will generate an interrupt.

c, TACCR0 The CCIFG flag has the highest interrupt priority of timer A and has a dedicated interrupt vector.

The TACCR0 CCIFG flag is automatically reset when the TACCR0 interrupt is entered.

d, TACCR1 CCIFG, TACCR2 CCIFG, and TAIFG flags share an interrupt vector. Interrupt vector register TAIV

Used to determine which of them requires a response interrupt. The highest priority interrupt generates a number in the TAIV register (see

Register description), this number is a specified number that can be identified in the program and automatically entered into the corresponding subroutine. No timing

The A interrupt will not affect the value of TAIV.

Reading and writing to TAIV automatically resets the highest priority pending interrupt flag. If another interrupt flag is set, at the end

After the original interrupt response, the interrupt response occurs immediately. For example, when the interrupt service routine accesses TAIV,

The TACCR1 and TACCR2 CCIFG flag bits are set and the TACCR1 CCIFG is automatically reset. RETI in the interrupt service routine

After the command is executed, the TACCR2 CCIFG flag will generate another interrupt.

Fourth, the capture mode of TimerA

1. Set: CAP=1 select capture, CCISx bit set capture signal source, CMx bit select capture edge, rise, fall, or rise and fall

capture.

2. If a second capture occurs before the first captured value is read, the capture compare register will generate an overflow logic, COV.

The bit is set at this time, as shown in Figure 8-11, the COV bit must be cleared by software.

Five, the register

1, TACTL: TimerA Control Register

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TASSELx: TA clock source selection

0: TACLK; 1: ACLK; 2: SMCLK; 3: INCLK

IDx: Input crossover, divided by clock source and then input into TimerA

0/1/2/3: 1/2/4/8 frequency division

MCx: Mode Control

0: stop timer; 1: increase mode, the timer counts to TACCR0;

2: continuous mode, the timer counts to 0xFFFF; 3: increase and decrease mode, 0->TACCR0->0

TACLR: Timer clear bit. This bit will reset the TAR, clock division and count direction. The TACLR bit is automatically reset and the value is read as 0.

TAIE: TA interrupt allowed. This bit allows TAIFG interrupt request

0: interrupt disabled; 1: interrupt enabled

TAIFG: TA interrupt flag

0: no interrupt pending; 1: interrupt pending

2, TAR: TimerA count register

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3, TACCTLx: capture comparison control register

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CMx: Capture mode

0: not captured; 1: rising edge capture; 2: falling edge capture; 3: rising and falling edges are captured

CCISx: Capture comparison selection, this bit selects the input signal of TACCRx

0: CCIxA; 1: CCIxB; 2: GND; 3: VCC

SCS: Synchronous capture source, this bit is used to synchronize capture communication and clock

0: Asynchronous capture; 1: Synchronous capture

SCCI: Synchronous capture/compare input, the selected CCI input signal is latched by the EQUx signal and can be read by this bit

CAP: Capture mode

0: comparison mode; 1: capture mode

OUTMODx: Output mode bit. These modes are invalid for TACCR0 due to EQUx= EQU0 in modes 2, 3, 6, and 7.

0: value of OUT bit; 1: set; 2: flip/reset; 3: set/reset

4: flip; 5: reset; 6: flip/set; 7: reset/set

CCIE: Capture compare interrupt enable bit, this bit allows the corresponding CCIFG flag interrupt request

0: interrupt disabled; 1: interrupt enabled

CCI: Capture comparison input. The selected input signal can be read by this bit

OUT: For output mode 0, this bit directly controls the output state.

0: output low level; 1: output high level

COV: Capture overflow bit. This bit indicates that a capture overflow has occurred. The COV must be reset by software.

0: no capture overflow occurs; 1: capture overflow occurs

CCIFG: Capture compare interrupt flag

0: no interrupt pending; 1: interrupt pending

4, TAIV: TimerA interrupt vector register

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The value of the register:

0: no interruption pending;

2: Capture comparison 1 TACCR1 CCIFG;

4: Capture comparison 2 TACCR2 CCIFG;

0xA: Timer overflow TAIFG

5.MSP430 interrupt nesting mechanism

(1) 430 defaults to turn off interrupt nesting unless you open the total interrupt EINT again in an interrupt routine.

(2) When entering the interrupt program, as long as the interrupt is not opened again in the interrupt, the total interrupt is turned off. At this time, the interrupt is not executed regardless of whether the priority of the current interrupt is higher or lower.

(3) If the total interrupt is opened in interrupt A, it can just respond to the subsequent interrupt B (regardless of whether B's priority is higher or lower than A), and B continues execution. Note: Entering interrupt B will also turn off the total interrupt. If the interrupt program C is required to be executed during the execution of the B interrupt program, the total interrupt will also be turned on. If there is no need to respond to the interrupt, then the interrupt will not be opened, and B will jump out after the execution. When the interrupt program enters the A program, the total interrupt is automatically turned on.

(4) If the total interrupt is opened in the interrupt, and there are multiple interrupts at the same time, it will be executed according to the priority. That is, the interrupt priority will only be used when multiple interrupts arrive at the same time! The interrupt service does not execute the preemption principle. .

(5) For single-source interrupts, the system hardware automatically clears the interrupt flag bit as long as the response is interrupted. For the comparison/capture interrupt of the TA/TB timer, as long as TAIV/TBIV is accessed, the flag bit is automatically cleared; for multi-source interrupts Manually clear the flag bit, such as the P1/P2 port interrupt, manually clear the corresponding flag. If the interrupt is opened with "EINT();" in this interrupt, and there is no clear flag before the interrupt is turned on, the same interrupt will continue. Embedding causes a stack overflow to cause a reset, so in such an interrupt it is necessary to clear the flag to open the interrupt switch.

6. About MSP430 Interrupt Mechanism - My Understanding

Due to the invitation of DC, I wrote a letter about the interruption. I also contacted 430 and soon I could only share my experience with my own family. If there is any leak, please forgive me. I will not go into the interrupts introduced in the MSP430 user manual. You can read the User Guider. I am mainly talking about the books that are not available in the book, or the points are not transparent. hope its good for U.S..

Interrupt nesting, priority

The control bit of the 430 total interrupt is the GIE bit in the status register (this bit is in the SR register). When this bit is in the reset state, all maskable interrupts will not respond. Maskable interrupts are divided into single interrupt sources and multiple interrupt sources. The single interrupt source generally responds to the interrupt service routine interrupt flag bit automatically cleared, while the multi-interrupt source requires that the interrupt flag bit be cleared after a certain register is queried. Since the first MCU that most people are exposed to is usually 51, 51 MCU CPU in response to a low priority interrupt program, if a higher priority interrupt occurs, the MCU will perform high priority, this process has been generated Interrupted nesting. The 430 MCU is different. If the low priority interrupt service request is responded to, even if a higher priority interrupt service request is received, the 430 will ignore it until the low priority interrupt service program is executed. Priority interrupt. This is because when the 430 responds to the interrupt routine, the total interrupt GIE is in the reset state. If a nesting similar to 51 is generated, the GIE bit can only be set again in the interrupt function.

2. Timer TA

TimerA has 2 interrupt vectors. TIMERA0, TIMERA1

TIMERA0 only counts overflow for CCR0

After TIMERA1 re-query TAIV, it can be known whether it is CCR1, CCR2, or TAIFG. As for when TAIFG is set, it depends on the mode of TA work.

See the user manual for details. Another point is that the TA itself has a PWM output function, so there is no need to borrow the interrupt function. On this issue, it is often the case that applying the detour is how to combine the timing of sampling with TA and AD. Many people do this by opening AD in the TA interrupt. This is not suitable, because the 430 ADC10, ADC12 (SD16 is unfamiliar, no voice) module has pulse sampling mode and extended sampling mode. As long as the AD is selected by the TA to trigger the sampling, and then set the TA to the PWM output mode, of course, the output PWM wave is a special function pin, but here it does not need to be output, so the pin settings do not have to be taken care of. What is worth paying attention to is the frequency of the PWM, which is the sampling rate of your AD.

3. Watchdog reset

The watchdog has 2 working modes: timer, watchdog

In the timer mode, the WDTIFG has a flag reset automatically in response to the interrupt service routine. In the watchdog mode, this flag can only be cleared by software. But how do you tell if the reset is caused by the timing overflow of the WDT operation in the watchdog mode, or is it caused by a watchdog write key error?....................................

The answer is that there is no way, at least I have not seen any methods, and I have not seen any way around people. If anyone knows how to thank you for sharing.

4. Some people often ask the role of MOV.B #LPM0,0(SP) of this statement. If you are in the LPM0 standby before entering the interrupt function, if you want to enter the LPM3 standby after executing the interrupt function, write MOV.B #LPM3 in the interrupt function, SR is invalid. Because 430 will push the PC and SR when the interrupt is entered, (the SR holds the low power mode setting). Even if you write MOV.B #LPM3, SR, the SR will be reset to the stack when exiting the interrupt. For low power consumption 0, to achieve this, only the SR settings in the stack can be changed: MOV.B #LPM0,0(SP).

5 interrupt vector:

The interrupt vector of 430 is FFE0H-FFFFH. A total of 32 bytes is the last segment of FLASH. The FLASH of 430 is large or small, but the last address is definitely FFFFH (except for large FLASH exceeding 64K), so their starting address is Not the same, and the general IAR default compilation is to put the program at the beginning of the FLASH (excluding the information segment).

One question that is worth clarifying is: What is the interrupt vector? The interrupt vector is actually the memory location that holds the entry address of the interrupt function. Just like the 2 bytes of FFFEH+FFFFH is the reset interrupt vector, then it stores the starting address of the main function in FLASH. If the main function is stored in the FLASH block starting from 0x1100, then you will find FFFFH stores 0x11, FFFE stores 0x00. Other TimerA, ADC12, all the same. It's just that the length of the program you write each time is different, and the location of the interrupt function is different. The IAR compiler will fix it for you, and then burn this address to the corresponding interrupt vector when you use JTAG to program. Because the address of the interrupt function can be customized by the user, IAR can also be compiled automatically, so this address is known to the source code developer, others do not know, BSL is the content of the 32-byte interrupt vector. The password for the particularity setting. However, there are a few things that are unchanged in 430. After the condition that triggers the interrupt is satisfied, where does it go to address the entry address of the interrupt service function, TI is solidified when it does 430, and is dead. For example, when power-on reset, it knows to go to FFFE, FFFF unit to find the address, not to FFE0, FFE2 to find the address, this mapping relationship is 430 curing unchanged. Sometimes you just need to change the "interrupt vector", what should I do? The 430FLASH program will sometimes encounter this problem from the upgrade, the method is to do a jump operation in the original default interrupt vector table of 430, the same above Reset as an example:

ORG 0x2345

PowerReset: mov.w &0xFCFE, PC

..............................

..............................

ORG 0xFFFE

DW PowerReset

In this case, 0xFCFE is quite a mapping of 0xFFFE. This is in the TI application report of the 430 program self-upgrading.