21ic Tensilica today announced the launch of an image and video data processor (DPU) IVP, which handles complex images in mobile handsets, tablets, digital television (DTV), automotive, video games and computer vision-based applications. Ideal for video signals. The IVP DPU has achieved breakthroughs in power and performance, and has produced many unprecedented applications based on programmable processors. IVP is supported by a number of third-party application developers, porting leading image applications to the IVP platform, including innovative multi-frame image capture, video pre- and post-processing algorithms, and evolving new technologies such as video stabilization and high dynamics. Range (HDR) imaging, high dynamic range video, face recognition and tracking, low illumination image enhancement, digital zoom, and gesture recognition. This article refers to the address: http:// The IVP digital signal processor has a unique instruction set for image and video pixel processing. The IVP single instruction can perform at least 16 16-bit pixel operations compared to a single-transmitted master CPU. Its composite instructions deliver 10-20 times better performance and lower power consumption. The IVP's rich instruction set has more than 300 image/video-specific vector instructions that can perform 32 or more 16-bit pixel processing operations per cycle. According to Will Strauss, president and chief DSP analyst at Forward Concepts, "As the number of mobile cameras increases, so does the demand for advanced processing of video and images. This load should be diverted from the host processor to ensure optimal performance. And the longest battery life. As the pace of innovation in image and video processing accelerates, Tensilica's IVP processor can help customers efficiently design dedicated algorithmic acceleration chips, enabling faster market-based and lower overhead for upgrade algorithms. ." Chris Rowen, founder and chief technology officer of Tensilica, said: "Consumers need imaging capabilities that are as good as HDR, but current processing technology is too slow, and the interval between shots takes a few seconds. Users want speeds up to 50 times, and Tensilica can provide What consumers want: instant, high-quality image and video capture. The IVP architecture supports ultra-high-quality image and video capture with advanced single-frame and multi-frame processing capabilities to accommodate the increasing sensor resolution. It's an exciting new product that is ready for the future." Efficient processor architecture Tensilica's IVP is a 4-way VLIW (very long instruction word) architecture that provides high parallelism, seamless mixing of long and short code instructions, and supports 32-way vector SIMD (single instruction, multiple data) operations. To keep up with fast-paced resolution and single-frame rate requirements, the architecture includes an integrated DMA (Direct Memory Access) transfer engine with throughput of up to 10 GB / sec. The local memory has a throughput of 1024 bits per cycle (64*16 pixels/cycle). IVP also has a number of unique image processing features that accelerate 8-bit, 16-bit, and 32-bit pixel data and video sample processing. The energy efficiency of IVP is very high. Under the 28nm HPM and RVT processes, the automatic synthesis and place-and-route process are used to complete the overall image processing of 1080p30 frame 16bit pixels with a power consumption of only 10.8 mW. Overall image processing is the most commonly used algorithm for face and object detection and gesture recognition. The high performance of IVP is reflected in the ability to implement complex algorithms such as motion detection and normalized cross-correlation operations, often used in high-precision module and feature matching and optical processing. Taking motion detection as an example, a 256*16 pixel search range and a 9*3 pixel module size are used to process 16-bit data of 1920*1080 pixels, and 142 points can be found in each cycle of the IVP. The 32-bit precision normalized cross-correlation processing of 16-bit pixel data can complete the calculation of 1 million 8*8 modules per second. software Many companies' patented images and computer vision processing algorithms can run smoothly on IVP because IVP has the C language programming mode common to TensilicaDPU. Tensilica has also established a network of partners to provide customers with portable, efficient third-party image processing algorithms. Companies that have ported their advanced image processing algorithms to IVP DPUs include Almalence, Irida Labs, Dream Chip Technologies, and Morpho. EugenePanich, president of Almalence, said: "Tensilica's advanced tool suite makes it easy to program your own algorithms for higher performance and differentiation. It's a pleasure to port software algorithms to Tensilica's IVP processor, Tensilica The compiler has powerful performance and is the best tool we have ever used. Tensilica's entire toolchain is of exceptional quality." Irida Labs CEO Vassilis Tsagaris said: "We are very pleased to be working with Tensilica. Compared to other platforms, IVP has greatly improved the performance of our embedded vision applications, such as the power efficiency of video stabilizers. IVP is shunt image processing. The best choice for the load." Differentiation customization Tensilica's IVP DPU can be further customized with Tensilica's patented processor configuration technology. The process of designing a DPU is fully automated, and each DPU has a matching software toolchain support. The toolchain includes an optimized compiler, linker, assembler, and debugger, as well as a corresponding fast instruction set simulator. Availability The first batch of customers received IVP delivery last year, and the IVP DPU is currently widely licensed. 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