The most advanced analog and RF circuits are currently being widely used in SoCs for consumer electronics, wireless communication devices, computers and network equipment. They present a range of verification challenges that are often not fully addressed by traditional SPICE, FastSPICE, and RF emulation software. These challenges include: design complexity of more than 100,000 devices, clock frequencies greater than a few GHz, nanoscale CMOS process technology, low power consumption, process variations, very significant nonlinear effects, extremely complex noise environments, and Wireless/wired communication protocol support issues.

These challenges have not existed in the development of most of today's traditional circuit simulation software. In many cases, the verification of today's analog and RF circuits prior to tapeout is often a matter of convergence and accuracy. The existing verification process does not keep up with the complexity of the design, so for a fully custom analog/RF subsystem chip, the design team often takes weeks or even months to verify. Designers tend to use overly conservative design methods, resulting in less than fully optimized designs and increased verification time. Therefore, the lack of analog/RF verification technology is the main reason for the delay in mass production of these chips.

Traditional SPICE simulators are no longer sufficient. New verification tools require SPICE to provide high-precision noise analysis, faster verification speeds, and increased capacity. Berkeley Design Automation's precision circuit analysis tools demonstrate the ability to solve today's complex verification problems. This article reviews the problems with analog/RF verification techniques in SoCs for consumer, wireless, computer, and networking applications, and explores how new technologies can help leading semiconductor companies significantly reduce product verification time and quickly get into volume production.

Great challenge

The verification process based on SPICE simulation is very effective for small-scale analog/RF modules. However, due to the increasing number of analog functions to be integrated in the SoC, and the emergence of new functional modules in the portable wireless and consumer device markets, the complexity of analog/RF modules is growing at a high rate. Traditional verification processes for small analog/RF modules have not been effectively applied to complex large analog/RF circuits. Simulations often take days to weeks, and in many cases, they don't even converge.

Analog circuits have grown from hundreds of devices to more than 10 million devices today. Design is now divided into multiple layers and multiple modules, which typically integrate passive components

On the same substrate. Therefore, the emulator needs the ability to perform functional simulations of the entire circuit. Currently, the circuit frequency has increased from MHz to several GHz. Periodic analysis is an important requirement for many high speed analog circuit applications. The simulator needs to handle transient and periodic analysis well to better predict the actual performance of the chip.

In addition, the current RF circuit is invariably switched to multiple operating frequencies, and the difference between frequencies can reach several orders of magnitude, such as a transceiver chip integrated with a VCO (Voltage Controlled Oscillator), a mixer, and the like. The simulator must be able to perform transient analysis efficiently to accommodate circuits that have multiple operating frequencies and that vary widely in frequency.

The continuous development and evolution of process technology is another reason for the increasing problem of verification. Analog and RF circuits have evolved from previous micron-scale processes such as bipolar processes to today's CMOS nanoscale processes. In nanoscale processes, variations in process parameters between wafers and wafers can greatly affect circuit performance and yield. Auto-calibration techniques can help solve this problem, but at the cost of additional design complexity and design area. Therefore, for medium-sized circuits, the simulator needs to have the accuracy and high performance of SPICE for various process angles and Monte Carlo analysis.

In these high-performance complex circuits, interconnects and PCBs can significantly affect the performance of the circuit at GHz, especially in nanoscale CMOS processes. Parasitic parameter analysis is necessary to identify sensitive modules and verify their interconnections in the surrounding environment. Therefore, for a circuit with multiple modules, the simulator needs to have the ability to perform efficient parasitic extraction after layout like SPICE, and also includes processing of PCB layout.

Finally, external noise caused by device intrinsic noise (such as thermal noise and flicker noise) and other digital/analog/RF circuits has evolved into a first-order effect. The noise of the device can significantly affect important analog and RF circuit blocks such as ADCs, VCOs, PLLs, and more. The simulator must be able to provide accurate internal and external analysis, including random noise sources and sources of noise.

The main complaint from the design team is that traditional SPICE simulation processes that work well for small analog and RF circuits are no longer sufficient for complex module designs and full circuit verification. For small module designs, designers rely on transistor-level SPICE simulation to fully verify their small circuit blocks. They typically perform circuit simulation, post-layout simulation, parametric variation analysis (process angle and Monte Carlo analysis), as well as package inductance and transmission line effect analysis, noise analysis (determined thermal and flicker noise), and periodic analysis of RF circuits. . These simulations can guarantee the function and performance of the circuit, and for small modules, the risk of the chip not working can be greatly reduced.

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