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1.Found clock-sensitive change during active clock edge at time
Cause: Clock-sensitive signals (eg, data, allowed end, clear, synchronous load, etc.) in the vector source file change at the edge of the clock at the same time. The clock-sensitive signal cannot be changed on the clock edge. The consequence is that the result is incorrect.
Action: Edit vector source file
2.Verilog HDLassignment warning at : truncated value with size to match size of target (
Reason: In the HDL design, the number of bits of the target is set, eg: reg[4:0] a; and the default is 32 bits. Decide the number of bits to the appropriate size: If the result is correct, there is no need to correct it. If you do not want to see this warning, you can change the set number of digits
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
Cause: The output port is no longer functional after synthesizer optimization
4.Following 9 pins have nothing, GND, or VCCdriving datain port -- changes to this connectivity may change fitting results
Cause: Pin 9 is empty or grounded or connected to the power supply. Measures: Sometimes the output port is defined, but the output is directly assigned '0', it will be grounded, and assigned '1' to the power supply. If these ports are used in your design, you can ignore these warnings.
5.Found pins functioning as undefined clocks and/or memory enable
Reason: It is your PIN as a clock that has no constraint information. You can do this with the appropriate PIN. Mainly refers to some of your pins that act as clock pins in the circuit, such as the flip-flop clk pin, which has no clock constraint, so Quartus II
"clk" as an undefined clock.
Action: If clk is not a clock, add "not clock" as the constraint; if it is, you can set it in the clock setting
Join in; in some cases where the clock requirement is not very high, you can ignore this warning or modify it here: Assignments>Timing analysis settings...>Individual clocks...>...
Note that only one clock pin can be selected in the Applies to node. The required fmax is usually 5% higher than the required frequency. It does not need to be too tight or too loose.
6.Timing characteristics of device EPM570T144C5 are preliminary
Reason: Because MAXII is a relatively new component in QuartusII timing is not the official version, wait for the service pack
Action: Only affect Quartus's Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Action: Change the on in timing setting&Option-->More Timing Setting-->setting-->Enable Clock Latency in setting to OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
Reason: Violation of the steup/hold time. It should be post-emulation. See if the waveform setting matches the clock edge with steup/hold.
Time Measures: Adding registers in the middle may solve the problem
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
Cause: The clock jitter is larger than the data delay. When the clock is fast, this problem occurs if there are too many levels of if, etc., but this problem is mostly seen in the highest frequency of the device: setting-->timing Requirements&Options-->Default required fmax Change some, such as to 50MHZ
10.Design contains input pin(s) that do not drive logic
Cause: The input pin has no drive logic (drives other pins) and all input pins require input logic measures: If this situation is intentional, ignore it, if unintentional, input the logic drive.
11.Warning :Found clock high time violation at 8.9ns on node 'TEST3.CLK'
Cause: The retention time of the PLS input in FF is too short. Measures: Set a higher clock frequency in FF
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Cause: If you use a CPLD with only one set of global clocks, the other clock generated by dividing by the global clock is treated as a signal in the wiring, and a low clock skew (SKEW) cannot be guaranteed. It will cause the timing circuit working on this clock to be unreliable, and even each time the wiring produces different problems.
Action: If you use an FPGA chip with more than two sets of global clocks, you can use the second global clock as another clock to solve this problem.
13.Critical Warning: Timing requirements were not met. See Report window for details.
Reason: timing requirements are not met,
Action: Double-click the Compilation Report-->Time Analyzer-->red part (such as clock setup:'clk', etc.)
--> Left-click the list path to see fmax's SLACK REPORT and resolve it according to the prompts. There may be a problem with the program's algorithm or fmax settings.
14.Warning: Can't find signal in vector source file for input pin |whole|clk10m
Cause: This time because all your input signals are not in your vector source file
(input pin) added to each input requires an excitation source
15.Can't achieve minimum setup and hold requirement along path(s). See Report window for details.
Cause: The time-series analysis found that a certain number of paths violate the minimum setup and hold time, which is related to clock skew, which is usually due to multiple clocks: use the Compilation Report-->Time Analyzer-->red part (eg, clock hold: 'clk', etc.) Watch if the hold time is negative or the setup time is negative in slack. Then add the clock name (from node finder) in : Assignment-->Assignment Editor-->To, add the Assignment Name Multicycle and Multicycle Hold options related to multiple clocks, such as hold time is negative, which causes Multicycle hold values ​​to be >multicycle, such as 2 and 1.
16: Can't analyze file -- file E://quartusii/*/*.v is missing
Cause: Attempting to compile a non-existent file, the file may be renamed or removed: No matter what, it has no effect
17.Warning: Can't find signal in vector source file for input pin |whole|clk10m
Cause: Because all of your input signals are not in your vector source file (input
Add) for each input requires an excitation source
18.Error: Can't name logic function scfifo0 of instance "inst" -- function has same name as current design file
Reason: The name of the module and the name of the project are renamed. Action: Change one of the two names, generally change the name of the module.
19.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
Reason: The module was not generated in this project, but was generated by copying the schematics and source programs of other projects directly, instead of using QUARTUS to add the files to this project. Measures: No need to bother, does not affect the use of
20.Timing characteristics of device are preliminary
Reason: The current version of Quartus II only provides preliminary timing analysis of the device: If you insist on using the current device, ignore this warning. Further timing feature analysis will be refined in subsequent versions of Quartus.
21.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Reason: Use the analyze_latches_as_synchronous_elements setting to allow the Quartus II to analyze synchronous latches, but current devices do not support this feature: Don't bother. Timing analysis may analyze the latch into a loop. But it does not necessarily analyze correctly. The consequences may cause the display to alert the user: change the design to eliminate the latch, but the actual does not really matter
22.Warning:Found xx output pins without output pin load
Reason: No load capacitance specified for output correction Solution: This function is used to estimate the TCO and power consumption and can be ignored. You can also specify the load capacitance for the corresponding output pin in the Assignment Editor to eliminate the warning.
QuartusII FPGA Error Collection
1) Error: Can't continue timing simulation because delay annotation information for design is missing.
Cause: Incomplete compilation is also possible if only functional simulation is required, but the timing simulation must be fully compiled (ie the purple solid triangle symbol on the toolbar).
The full simulation consists of four modules: Synthesis, Fitter, Assember, and Timing Analyzer. The task pane has success flags (checkmarks).
2) During the download run, the following error appears:
Warning: The JTAGcable you are using is not supported for Nios II systems.
You may experience intermittent JTAG communication failures with this cable. Please use a USB Blaster revision B.
The .sof file was downloaded to the development board before running, but the above problem still occurs.
Solution: In the configuration, after run, configure, select target connection, in the last item: NIOS II Terminal Communication Device, select none (not Jtag_uart) If you use USB Blaster, you can choose Jtag_uart.
After that run ok!
3)Error: Can't compile duplicate declarations of entity "count3" into library "work"
This error is generally caused by the duplicate of the name of the schematic file and the name of a device in the figure. Therefore, changing the name of the schematic file can be saved.
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1.Found clock-sensitive change during active clock edge at time on register ""
Cause: Clock-sensitive signals in the vector source file (eg, data, enable side, clear, synchronous load, etc.) change at the same time on the edge of the clock. The clock-sensitive signal cannot change on the clock edge. The consequence is that the result is incorrect. .
Action: Edit the vector source file
2.Verilog HDL assignment warning at : truncated with size
< number> to match size of target (
Cause: The number of bits of the target was set in the HDL design, eg: reg[4:0] a; and the default is 32 bits.
Decide the number of bits to the right size
Measure: If the result is correct, there is no need to correct it. If you do not want to see this warning, you can change the set number of digits.
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
Reason: After the optimizer is optimized, the output port is no longer functional
4.Following 9 pins have nothing, GND, or VCCdriving datain port -- changes to this connectivity may change fitting results
Cause: There are 9 feet are empty or grounded or connected to the power supply measures: Sometimes the output port is defined, but the output is directly assigned '0', it will be grounded, assigned '1' to the power supply. If your design These ports are used like this, so you can ignore these warnings
5.Found pins functioning as undefined clocks and/or memory enable
The reason: It is your PIN as a clock that has no constraint information. It is OK to set the corresponding PIN. It means that some of your pins act as clock pins in the circuit, such as the flip-flop clk. Pins, but this pin has no clock constraints, so QuartusII uses "clk" as an undefined clock.
Action: If clk is not a clock, add "not clock" as the constraint; if it is, you can use the clock
The setting is added; In some cases where the clock requirement is not high, you can ignore this warning or modify it here: Assignments>Timing analysis settings...>Individual
Clocks...>...
6.Timing characteristics of device EPM570T144C5 are preliminary
Reason: Because the MAXII is a relatively new component in the QuartusII timing is not the official version, wait for the service pack
Action: Only affect Quartus's Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Action: Set Timing Requirements&Option-->More Timing in setting
Setting-->setting-->Enable Clock Latency change to OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
Reason: Violation of the steup/hold time. It should be post-emulation. See if the waveform setting matches the clock edge.
Steup/hold time Action: Adding registers in the middle may solve the problem
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
Cause: The clock jitter is larger than the data delay. When the clock is very fast, this problem will occur if there is too many levels of if, etc., but this problem is mostly seen in the highest frequency of the device: setting-->timing Requirements&Options-->Default required fmax to change some, such as to 50MHZ
10.Design contains input pin(s) that do not drive logic
Cause: The input pin has no drive logic (drives other pins) and all input pins require input logic measures: If this situation is intentional, ignore it. If not, enter the logic drive.
11.Warning: Found clock high time violation at 8.9ns on node 'TEST3.CLK'
Cause: The retention time of the PLS entered in FF is too short. Measures: Set a higher clock frequency in FF
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Cause: If you use a CPLD with only one set of global clocks, the other clock generated with the global clock divided down is treated as a signal in the cabling, which does not guarantee a low clock skew (SKEW). This will cause work on this clock. The timing circuit is unreliable, and even the problem of each wiring is different.
Measures: If you use an FPGA chip with more than two sets of global clocks, you can use the second global clock as another clock to solve this problem.
13.Critical Warning: Timing requirements were not met. See Report window for details.
Reason: Timing requirements are not met,
Action: Double-click the Compilation Report-->Time Analyzer-->red part (eg clock
Setup:'clk', etc.) --> Left click on list path to see fmax's SLACK REPOR and then solve it according to the hints. It may be an algorithm problem of the program.
14.Can't achieve minimumsetup and hold requirement along path(s). See Report window for details.
Cause: Timing analysis finds that a certain number of paths violate the minimum setup and hold time, which is related to clock skew, which is usually due to multiple clocks: Use the Compilation Report-->Time Analyzer-->red part (eg clock
Hold:'clk', etc.), Observed in slack is whether hold time is negative or setup time is negative.
Then add :from node finder to Assignment-->Assignment Editor-->To. Add multiple clock-related Multicycle and Multicycle Hold options to Assignment Name. If Hold time is negative, Multicycle hold value can be enabled. >multicycle, as set to 2 and 1.
15: Can't analyze file -- file E://quartusii/*/*.v is missing
Cause: Attempting to compile a non-existent file, the file may be renamed or removed: No matter what, it doesn't matter
16.Warning: Can't find signal in vector source file for input pin |whole|clk10m
Cause: Because all of the input pins are not included in your vector source file, an excitation source is required for each input.
17.Error: Can't name logic scfifo0 of instance "inst" -- has same name as current design file
Cause: The name of the module and the name of the project are duplicated. Action: Change one of the two names, usually change the name of the module.
18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
Reason: The module is not generated in this project, but is generated by copying the schematics and source programs of other projects directly, instead of using QUARTU to add S files to this project. Measures: No need to bother, does not affect the use of
19.Timing characteristics of devices are preliminary
Cause: The current version of Quartus II only provides preliminary timing analysis of the device: If you insist on using the current device, you do not need to pay attention to this warning. Analysis of further timing features will be perfected in subsequent versions of Quartus.
20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Reason: The analyze_latches_as_synchronous_elements setting can be used by Quartus II to analyze synchronous latches, but current devices do not support this feature measure: No need to worry about it. Timing analysis may analyze the latches into loops. But it may not be analyzed correctly. The consequences may be Causes display to alert user: Change design to eliminate latches
21.Warning:Found xx output pins without output pin load
Cause: No load capacitance was specified for the output controller. Measures: This function is used to estimate the TCO and power consumption. It can be ignored. You can also specify the load capacitance for the corresponding output pin in the Assignment Editor to eliminate the warning.
22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Cause: A traveling wave clock or a gated clock is used, and the output of the flip-flop is reported as the clock by the clock.
The output of the combinational logic will be reported to the gated clock when the clock is used. Measures: Do not use the output of the flip-flop as the clock. Do not use the output of the combinational logic as the clock. If it is designed in this way, the warning is ignored.
23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments
Reason: There are both blocking and non-blocking assignments in an always block
24.Warning: Can't find signal in vector source file for input pin |whole|clk10m
Cause: This is because your vector source file does not include all of the input pins. There is an excitation source for each input.
25 Warning:Output pins are stuck at VCC or GND
If you just want some output to be fixed high or low or don't care, don't worry about it, otherwise check the code. This output actually has no meaning.
26.Warning (10208): honored full_case synthesis attribute - differences
Between design synthesis and simulation may occur
/* synopsys full_case */ ; D2g/ w&N6 S*p6 T; W!C/`8 M
The meaning is: } #Q #_) p) U' @, ] / ~; b
Tell synthesis software that your case is almost a full case, and you (the designer) can guarantee that the case is not listed
Branching will never happen. 8r0 a! o- T! h8l+ O.{
Purpose: Tell synthetic software not to consider case branches that are not listed, for ease of simplification.
Limitations: Of course only Synopsys's synthetic software can understand! So it is not recommended, it is better to use default.
Disadvantages: Inconsistent simulation before and after, inconsistent results and expectations.
27:Warning: No exact pin location assignment(s) for 16 pins of 16 total pins
The defined pin is not connected to the external pin.
28: Warning: Ignored locations or region assignments to the following nodes
Warning: Node "78ledcom[4]" is assigned to location or region, but does not exist in design
The design did not mention "78ledcom[4]" and assigned pins to it.
Note: Sometimes the TCL script file needs to be modified after running, and some previously allocated pins are not needed after the modification. If there is no delete, this prompt will appear.
The solution: assignments->pins, you can delete the unused pins (TCL script file redundant pin assignment statement is also best to delete together).
PS: Until now, press F1 to see the help group when there are errors or warnings.
Quartus Common Warnings and Errors
1. Warning: VHDLProcess Statement warning at random.vhd(18): signal reset is in
Statement, but is not in sensitivity list
---- Did not put singal into process ()
2. Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock
-=----- May be that the trigger generated in the design has no enable
3. Error: VHDLInterface Declaration error in clk_gen.vhd(29): interface object
"clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------ Signal type is set incorrectly, out is defined as buffer
4. Error: Nodeinstance "clk_gen1" instantiates undefined entity "clk_gen"
------- Referenced instantiated component undefined entity -- entity "clk_gen"
5. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or
Gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable
"dataout" may not be assigned a new in every possible path through the Process
Statement. Signal or variable "dataout" holds its previous in every path with no
New assignment, which may create a combinational loop in the current design.
7. Warning: VHDLProcess Statement warning at divider_10.vhd(17): signal "cnt" is
Read inside the Process Statement but isn't in the Process Statement's sensivitity list
----- Lack of sensitive signals
8. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9. Warning: Reducedregister "counter_bcd7:counter_counter_clk|q_sig[3]" with
Stuck clock port to stuck GND
10. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked
By clock "class[1]" with clock skew larger than data delay. See Compilation
Report for details.
11. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked
By clock "sign" with clock skew larger than data delay. See Compilation Report
For details.
12. Error: VHDLerror at counter_clk.vhd(90): actual port "class" of mode "in"
Cannot be associated with formal port "class" of mode "out"
------ Both cannot be connected
13. Warning: Ignored node in vector source file. Can't find required node
Name "class_sig[2]" in design.
------ No testbench file has been written, or the value of the input variable has not been edited. Component declaration and mapping in testbench
14. Error: VHDLBinding Indication error at freqdetect_top.vhd(19): port "class"
In design entity does not have std_logic_vector type that is specified for the
Same generic in the associated component
--- There is no type defined by the current file in the associated component
15. Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"
Because signal does not hold its outside clock edge
16. Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17. Warning: Compiler packed, optimized or synthesized away node "temp[19]".
Ignored vector source file node.
---"temp[19]" was optimized out
18. Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------ Output signal has nothing to do with the input signal,
20. Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
21. Error: VHDLerror at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"
22. Error: VHDLAssociation List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not
Declared
------- Connection table error. The parameter "alarm" is assigned to the actual parameter. The parameter is not defined. The position of the actual parameter may be reversed. The parameter is specified before the actual parameter.
23. Error: Ignored construct behavier at period_counter.vhd(15) because of
Previous errors
-------- Error due to previous error
24. Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does
Not agree with its usage as std_logic type
-------- The definition of "alarm" is inconsistent with the type used
25Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement
With conditions that test for the edges of multiple clocks
------- There are two or more if(edge) conditions in the same process, (there can be a clock edge in a process)
26. Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at
Shift_reg.vhd(19)
27. can't infer register for signal "num[0]" because signal does not hold its
Outside clock edge
28. Error: Can't steps top-level user hierarchy
29. Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ---------- There are more than two assignment statements and cannot determine the value of "cs_in"
30. Warning: Ignored node in vector source file. Can't find required node
Name "over" in design.
--------------- The corresponding node "over" was not found in the source file.
31. Error: Can't access JTAG chain
Unable to find download chain
32. Info: Assuming node "clk" is an undefined clock
1. different smt machines with different smt feeders, but different model of the same brand machine can use the same feeder,like Panasonic Feeder.
2. Base on the size and types of components, smt feeder could be divided into three types : Tube feeder; Tray Feeder; Bulk Feeder.
Tape feeders with the different size such as 8mm, 16mm, 24mm, 32mm, 44mm, 56mm etc.
3. Base on the feeder condition, smt feeder also could be divided into four types: original new SMT feeder parts, used original SMT feeder parts, imitation/copy new SMT feeder parts, imitation/copy used SMT feeder parts,
Original feeder is made by original smt machine production manufacturers. Due to the large demand for smt feeder, currently there are many copy new feeders parts. Our feeders quality is also very great and looking forward to your cooperation!